(1) Field of the Invention
The present invention relates to a packet switch applied as a node apparatus in a variable length packet communication network and, more particularly, a shared buffer type variable length packet switch using a shared buffer memory as a memory for temporarily storing received packets.
(2) Description of the Related Art
In recent years, in the Internet protocol (IP) to which attention is paid, a message is transferred by using a variable length packet (IP packet) called IP datagram as a transfer unit. In a conventional node apparatus as an element of an IP packet network, received packets are switched to a destination path by a software process. To address a demand on higher speed of switching, a node apparatus for switching a packet by using a fixed length packet (data block) as a transfer unit has been proposed.
As a node apparatus for transferring IP packets at high speed, for example, the paper of “A 50-Gb/s IP Router”, Craig Partridge et al., IEEE/ACM TRANSACTIONS ON NETWORKING, Vol. 6, No. 3, June 1998 discloses a router having the configuration in which a plurality of line cards (line boards) for supporting a plurality of network interfaces and a forwarding engine card having a routing table are coupled to each other via, for example, a point-to-point type switch typified by a crossbar switch. Each of the line cards transmits a data block including a header of a received packet to the forwarding engine. A data block including new header information updated by the forwarding engine is returned to the line card on the packet input side. Each of the line cards on the input side forwards the data block including the new header information and the rest of the packet toga line card on the output side.
The paper discloses that each of the line cards on the input side decomposes a packet to linked pages (data blocks) of a 64-byte unit and transmits the pages, and each of the line cards on the output side assembles the received pages to a linked list indicative of a packet and transfers the assembled packet to a QoS processor. The QoS processor places the packet in a proper position in a transmission queue on the basis of the packet length, destination, and a flow identifier designated by the forwarding engine.
One of switches for forwarding received packets in a fixed length packet unit is an ATM (Asynchronous Transfer Mode) switch. In the ATM switch, a fixed length packet (ATM cell) of 53 bytes received from each of input lines is temporarily stored in a buffer memory, and the stored cell is routed to a specific output line determined by a connection identifier (VPI/VCI) included in the cell header. When the ATM switch adopts a shared buffer type structure in which a buffer memory is shared by a plurality of input lines, it is able to form a variable length queue for each of output lines in the buffer memory. Therefore, for example, even when cell trains heading for the same output line are simultaneously received from a plurality of input lines, as far as there is an available space in the shared buffer as a whole, received cells from the input lines can be buffered without discarding a part of them. A switch effectively using the memory resource can be therefore realized.
Japanese Unexamined Patent Application No. 11-261584 discloses a switch for a variable length message, which utilizes the advantages of the shared buffer memory. In the Prior technique, the shared buffer memory is divided into a plurality of memory blocks corresponding to messages in advance, and one available memory block is assigned to each of the received messages. Each message received from each input line is divided into a plurality of fixed length cells, and a group of cells belonging to the same message are sequentially stored in the same memory block.